1. Field of the Invention
The invention relates in general to a liquid crystal display module, and more particularly, to a liquid crystal display module with short-circuit protection for the test circuit.
2. Description of the Related Art
In order to reduce the failure rate of the polarizer during the manufacturing process of liquid crystal display (LCD), the original function test is re-scheduled forward. The pre-test for the substrate of thin film transistor (TFT) is now re-scheduled and is done prior to the pasting of the polarizer, so that faulty TFT glass substrates can be found earlier and the pass rate during the manufacturing process can be improved.
Referring to FIG. 1, a partial block diagram of the circuit layout according to a conventional test circuit. A number of indium tin oxide (ITO) leads (under ITO layer have others metal) 106a, 106b, 106c and 106d are deposited on one side of TFT glass substrate (not shown in FIG. 1) in equal distance. Test circuit 102 includes a number of metal wires 102a, 102b and 102c. Test circuit 102 is also deposited on the TFT glass substrate. Traces 104a, 104b, 104c and 104d are electrically connected to their corresponding ITO leads 106a, 106b, 106c and 106d. The trace 104 and test circuit 102 are electrically connected together via contact hole 112, while test circuit 102 and its corresponding ITO lead 106 are electrically connected together in a shortest straight line by trace 104.
Prior to the pre-test, the TFT glass substrate is electrically connected to a test unit 114 via test circuit 102 and is tested by test unit 114.
Referring to both FIG. 2 and FIG. 3A at the same time. FIG. 2 is a partial block diagram showing the connection between tape carrier package leads (TCP leads) and indium tin oxide (ITO) leads according to prior arts while FIG. 3A is a sectional view along the sectional line 3A–3A′ in FIG. 2. Test circuit 102 is covered up by a first passivation layer 308 for isolating and protecting the test circuit. Traces 104a, 104b, 104c and 104d are covered up by a second passivation layer 110. When the pre-test is completed, a laser beam is used to burn trace 104 and have it separated to form an electrically isolated region which is be further extended to form a laser cutting path 108. After that, TCP lead 202 is sealed to its corresponding ITO lead 106 on glass substrate 302 using heat sealing process.
Referring to FIG. 3A, the manufacturing process for sealing the TCP leads to the glass substrate is elaborated below. First, pasting an anisotropic conductive film (ACF) 306 on ITO lead 106b. Next, TCP lead 202b and ITO lead 106b are mounted together and pressed downward, so that TCP lead 202b is sealed and electrically connected to ITO lead 106b via ACF 306. Meanwhile, TCP and glass substrate 302 are connected together as well.
Referring TO FIG. 3A, TCP whose IC chips are not shown here includes three layers, namely, soft tape layer 310 which uses polyimide (PI) as the base material, copper plating layer 312, and solder resist layer 314, wherein TCP lead 202b is formed on copper plating layer 312 to be electrically connected to ITO lead 106b. 
Referring to FIG. 3B, an enlargement of region A in FIG. 3A. In the conventional process disclosed above, the laser cutting process performs an instant high-temperature heat treatment on trace 104. Consequently, trace 104 is melted and cut off to form a laser cutting path 108 whereby metal wire 102b is electrically disconnected from ITO lead 106. However, during the high-temperature melting process, trace 104b might spread over the top-face of second passivation 110 and leave metal remnants 316 thereon. When TCP lead 202b is to be sealed to ITO lead 106b, TCP lead 202b will contact with metal remnants 316 at the break-points on trace 104b resulting in short circuits. Under this circumstance, malfunction in TFT substrate will arise and lead to in a high rejection rate.